1. Field of the Invention
The present invention relates to an electronic parts loaded module, and more particularly, to a module loaded with electronic parts via projecting electroconductive electrodes on a circuit board, a method for manufacturing the same, and a device having such an electronic parts loaded module.
2. Description of Related Art
Conventional electronic parts include semiconductor devices such as silicon chips, resistor chips such as silicon substrates having resistors formed thereon, capacitor chips such as silicon substrates having multilayered dielectric elements coated thereon, and the like. The electronic parts loaded module has fine connections for effecting electric communications, which may cause the following problems when a significant difference in thermal expansion between the electric parts and the underlying substrate exists. The problems will be explained with respect to semiconductor devices hereunder, but they may be also produced with other electronic parts.
The semiconductor devices have been generally made with a number of connections disposed spacing from apart each other, the pitch of which has been made smaller and smaller. The tendency that the number of connection points per semiconductor device has been ever increasing has assisted in promoting that the connection pitches are made much finer. Typical examples of the semiconductor devices with fine connection pitches are integrated circuits for operating liquid crystal display devices. Moreover, it is difficult to provide a multi-layer circuit on a liquid crystal display substrate, so that connection terminals are formed to concentrate in the peripheral regions of an IC chip, which results in requiring further reduced pitches.
Means for connecting the connection terminals aligned straight along the periphery of the IC chip to a circuit board is generally wire-bondings or Tape Automated Bonding (TAB) with polyimide based tapes. However, the use of these means are limited due to connection pitches. The former is limited because of the dimensions of bonding tools, while the latter is limited because of the accuracy of processing copper foils.
As structures independent of the limitations as described above, one may make mention such structures as the surface of a semiconductor device facing that of the circuit board as called face-down or flip chip bondings. This structure requires generally projecting electrodes to ensure electrical communication and insulation between the semiconductor device and the circuit board. Of course, the projecting electrodes are not necessarily required. There have been proposed a structure using no projecting electrode as disclosed in Japanese Patent KOKAI (Laid-open) No. Hei 2-84747. Alternatively, there may be a structure having connecting means interposed between the semiconductor device and the circuit board as disclosed in Japanese Patent KOKAI (Laid-open) Nos. Sho 57-28337, Hei 2-54946, and Hei 2-82545.
In view of practical aspects such as cost, mass productivity and the like, however, the technique in which the projecting electrodes are formed are most reasonable. Therefore, a number of patents have been published with respect to projecting electrodes. They can be further classified depending upon which the projections are formed on, the semiconductor device or the circuit board. The techniques forming the projections on the side of the circuit board are disclosed in Japanese Patent KOKAI (Laid-open) Nos. Sho 61-245543, Sho 62-161187, Sho 63-40331, Sho 63-92036, Sho 63-220533, Hei 1-273327, Hei 1-281433, Hei 2-28340, Sho 62-35597, and Sho 63-70888. Particularly, in case the semiconductor devices are loaded only on the periphery of a large type circuit board as liquid crystal display devices, the number of the projections to be formed is fairly small relative to the surface area of the board to be used so that the use of the aforementioned structure is conceivably disadvantageous in cost.
In contrast, the structure where the projections are provided on the semiconductor device is more reasonable as described in a greater number of patent applications. As materials for the projections, Au (gold) is most popular to be found in many patent applications including Japanese Patent KOKAI (Laid-open) No. Sho 60-85545. Alternatively, the use of solders is one of remarkable examples making use of the higher ductility characteristic of the alloy. Japanese Patent KOKAI (Laid-open) Nos. Hei 2-37724, Sho 63-9136, Sho 62-287647, and Sho 63-122155 may be mentioned. In any case, soft materials are selected. As discussed hereinafter, first object is to relax the stress caused by a difference in thermal expansion between the semiconductor device and the circuit board. Plating is a generic technique for forming the projections, although the utilizing of wires has attracted interest as disclosed in Japanese Patent KOKAI (Laid-open) Nos. Sho 63-304587 and Sho 61-117846.
In any technique as described above, the spacing between the semiconductor device and the circuit board is inevitably reduced as the connection pitch is reduced. As a result, a greater stress is developed between the semiconductor device and the circuit board owing to the difference in thermal expansion therebetween. An attempt has been proposed to disperse and relax the stress by disposing a resin between the semiconductor device and the circuit board as described in NIKKEI MICRODEVICE, July 1989, pp. 46-47.
However, this structure suffers from a drawback of instability in its reliability depending upon the physical properties of the resin as pointed out in the Journal of Electronic Information Communicating Society, Vol. J73-C-II , No. 9, pp. 516-524 (1990.9). It is important, therefore, to provide a structure capable of achieving the relaxation of the stress without using resins.
A bump formed on an electrode pad has generally a circular cross-section in a plane. Alternatively, another technique where the cross-section in a plane of a bump formed has different dimensions in normally crossing directions, i.e., one larger diameter and the other shorter diameter can be mentioned as described in Japanese Patent KOKAI (Laid-open) Nos. Hei 2-170548 and Hei 1-243533. In the former, the bump is formed with solder to have an ellipse cross-section in a plane, the shorter axis of which is along the direction directing to the center of the chip as illustrated in Examples of the patent. However, this technique is for allowing the chip and the circuit board to abut with each other at high accuracy in their positions. In contrast, in the latter, projecting electrodes have a dumb-bell configuration in a plane. This is for enhancing not only the shear strength in the longitudinal direction of the bump, but also that in the direction of the shorter dimension. Both two techniques as described above employ solder, but they fail to take into consideration the relaxation of the thermal stress applied to the bump by deformation thereof.
When the bump is fromed to have a dumb-bell cross-section, the thermal stress imposed on the bump can be dissipated owing to flexure of the narrowed part of the bumb-bell shape. This scheme is disclosed in Japanese Patent KOKAI (Laid-open) No. Sho 61-43438. In this scheme, however, the bump does not have any anisotropy in rigidity.
As discussed above, the prior arts disclose no technique to essentially cope with the difficulty of avoiding the difference in thermal expansion between the electronic parts and the circuit board.